The PCRAM program focuses on the achievement of high density, high speed and high endurance for PCRAM devices. In relation to this, we investigate on:
Scaling limitations of PCRAM and related factors, and nano-phase change
For scaling limitation, we observe that the behaviour of a phase change material at nano-scale is different from bulk due to its changes in its crystallization temperature, its melting point, its mass density, its influences by the stress and also diffusion, etc which are all inter-related.
Nano phase change can be classified into 2 categories: 1) thin film related and 2) structure related. Film thickness and capping materials are key factors for thin film type, while structure shape, size and surrounding materials are critical parameters for structure type.
We have identified that the scaling limitation of PCRAM is ~ 5 nm.
Fig. 1 Factors of scaling limitation of phase change material
High density PCRAM through current reduction by material and structure engineering, multi-level and cross-bar architecture
For example, artificial phase change structures, e.g. Superlattice-Like (SLL), quantum dot, were proposed to manipulate phase change materials’ properties. PCRAM with SLL has demonstrated 60% reduction in RESET current and increased speed.
Fig. 2 Phase change memory incorporating Superlattice-Like (SLL) material
DRAM-like speed through material and device engineering
We have identified the cell size and interfacial effects on the phase change speed, and also found out that the material surface or interfaces will play an increasingly important role as the material size shrinks. We have demonstrated 400 ps RESET and 2.5 ns SET with 19 nm PCRAM.
Fig. 3 Comparing big cells (a) & (c) and small cells (b) & (d), additional interface carriers from small cells contribute to faster phase switching process
We are currently developing 1 Mb PCRAM chip with memory controller and advanced coding schemes for NVM-based green data centre application. In addition, we are continuously exploring new structures and new materials to improve its performances.
Fig. 4 (a) Wafer integrated with IC and (b) Chip layout